FPGA Implementation of Boolean Neural Networks using UML

This paper suggests a new approach for modeling of Boolean neural networks on fieldprogrammable gate arrays (FPGAs) using UML. The presented Boolean neural networks (BNN) allow a decreasing of the required number of configurable logic blocks (CLB) for the realizing of Boolean neuron. The element of BNN, called Boolean neuron, may be mapped directly to lookup table (LUT) and configurable logic block (CLB) of FPGAs. Our approach solves digital design problems especially with respect of the performance and gate count. In the examples through paper we describe the UML model of the BNN, its transformation, and the mapping to FPGAs.